The development of two-dimensional (2D) semiconducting materials has opened up new possibilities in the world of optoelectronics. These materials offer unique properties that could revolutionize the design of ultra-thin and tunable electronic components. However, despite their potential advantages over traditional bulk semiconductors, researchers have faced challenges in effectively integrating these materials with gate dielectrics. This issue has often led to the formation of interfacial traps that can quickly degrade the performance of transistors.
A recent collaborative effort between researchers at King Abdullah University of Science and Technology (KAUST), Soochow University, and other institutions worldwide has proposed a new approach to address this challenge. Their innovative design, detailed in a paper published in Nature Electronics, involves the use of hexagonal boron nitride (h-BN) dielectrics and metal gate electrodes with a high cohesive energy.
According to Yaqing Shen, the first author of the paper, experiments have shown that the use of platinum (Pt) as an anode in combination with h-BN stacks can significantly reduce the risk of dielectric breakdown. In fact, Pt/h-BN gate stacks have demonstrated a 500-times lower leakage current compared to transistors with gold (Au) electrodes. This exceptional performance has highlighted the potential of using chemical vapor deposited h-BN as a gate dielectric in 2D transistors.
Shen, along with Prof. Mario Lanza and their team, fabricated over 1,000 devices using h-BN gate dielectrics. Their evaluation revealed that h-BN was most compatible with high cohesive energy metals such as Pt and tungsten (W). To create transistors with a vertical Pt/h-BN/MoS2 structure, the researchers meticulously cleaned a SiO2/Si substrate before patterning the source and drain electrodes and depositing MoS2 to form the channel. The CVD h-BN film was then transferred to complete the structure.
In the final steps of the transistor fabrication process, the researchers patterned the Pt gate electrode and deposited it using e-beam evaporation. The clean van der Waals interface between MoS2 and h-BN in their transistor design has been instrumental in improving reliability and performance, minimizing defects, and enhancing gate control.
Shifting Perceptions on CVD h-BN as a Gate Dielectric
Contrary to previous beliefs, the research team has demonstrated that selecting the right metal electrodes, such as Pt and W, can effectively leverage CVD h-BN as a gate dielectric in 2D transistors. The clean van der Waals interface formed between MoS2 and h-BN enhances reliability and performance, challenging the notion that CVD h-BN is a subpar gate dielectric material.
The team’s innovative approach has shown promising results in reducing leakage currents and achieving a high dielectric strength of at least 25 MV cm-1. Through their research, they have paved the way for the development of reliable solid-state microelectronic circuits and devices using 2D materials. This breakthrough could inspire other research groups to explore similar strategies and materials, potentially leading to the creation of highly advanced 2D semiconductor-based devices.
Driving Innovation Towards Ultra-Small Transistors
Looking ahead, Shen and her colleagues plan to focus on developing ultra-small (nanoscale) fully 2D transistors to further push the boundaries of Moore’s Law. By continuing to explore the potential of 2D semiconductors and innovative device designs, the future of electronic components is poised for remarkable advancements. The collaboration between academia and industry in this field is crucial for driving innovation and shaping the next generation of electronic technologies.
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